Topics

• Correction: Elektronik Analyzes Ultra-Low Power Microcontroller Claims
• ScaleMark: EEMBC’s Benchmark Suite for Cloud and Scale-out Servers Enters Beta Stage
• Andes Technology Unveils a Mountain of CoreMark Certified Results
• Interesting CoreMark Discovery
• Renesas DevCon
• Light Reading’s Next Generation Network Components
• ARM TechCon
• Free Benchmark Downloads

Elektronik Analyzes Ultra-Low Power Microcontroller Claims

Correction: In September, our newsletter indicated that the following article was provided by Design Elektronik, when in fact it was produced by Elektronik as an Elektronik-Projekt, a unique set of articles with deep technical focus.
Dr. Claus Kühnel (Director Head of Embedded Systems at QIAGEN Instruments AG) and Frank Riemenschneider (Formerly editor at Elektronik, now editor-in-chief of Design & Elektronik) tested the claims of the ‘ultra-low power marketing messages’ of every well-known MCU vendor. This exercise was performed within Elektronik as an Elektronik-Projekt, a unique set of articles with deep technical focus. With the support of each vendor, Claus and Frank configured the microcontroller boards, built the EEMBC ULPBench software, and utilized EEMBC EnergyMonitor to make measurements. Their results were originally published in Elektronik 16/2015, starting on page 26 on August, 11th.

• German (original)
• English
• Chinese
• Japanese

ScaleMark: EEMBC’s Benchmark Suite for Cloud and Scale-out Servers Enters Beta Stage

EEMBC Beta version of its new cloud and scale-out server benchmark suite, ScaleMark, is ready. It focuses on web caching for the initial segment. This suite addresses the needs of ODMS, OEMS, and cloud and big-data users who deploy their applications in large distributed computer centers made up of clusters of servers. The industry has lacked a reliable, repeatable, portable, and architecture-neutral method to evaluate the latency and throughput of SoCs and associated servers for real-world cloud and big-data applications running at data centers – that all changes with ScaleMark. Interested in becoming a Beta tester (no charge) for ScaleMark? Contact Markus Levy

Andes Technology Unveils a Mountain of CoreMark Certified Results

Andes Technology Corporation, an EEMBC member since 2009, has just published officially-certified CoreMark results for its entire CPU product line (ranging from the 2-stage pipeline N705 CPU core, which achieved a CoreMark/MHz score of 3.32 to the 8-stage pipeline Andes N1337 CPU core that achieved a CoreMark/MHz score of 3.13). Check out the press release.

An Interesting CoreMark Discovery

Our lab just finished certifying CoreMark results for a member’s IP cores on an FPGA. Interesting that our lab obtained the exact result as the member - down to the 6th decimal. For example, on one core, the member obtained 91.512638, the lab also got 91.512638. Is this odd? Apparently not!

1. The CoreMark execution flow is fixed (i.e., there is no input data to change the flow)
2. Memory latency is 1 cycle, there is no other master contending, and the clock is synchronous. The program and data reside on I and D local memory.
3. There are no interrupts because no additional device activity is on-going in CoreMark.

However, there are situations when there could be variability. According to Mark Wallis of STMicro (co-chair of EEMBC’s IoT working group), the timer measuring the test’s run time can be one source of variability – if the timer clock and processor clock are asynchronous, there should be some variations. But if the clock is synchronous (as stated above), then any real clock frequency variation will not change the result since the timer frequency does not vary relative to the CPU frequency. For example, ST use a timer integrated in the ARM core (systick), so the clock is synchronous with the CPU clock. Nevertheless this timer wraps many thousands of times during a run, and generates an interrupt each time. Therefore, he expects interrupt latency to be slightly variable depending on the code being executed when the interrupt occurs. Furthermore, some rounding error occurs when converting timer count to seconds. By varying the number of iterations, you should see small differences in results. That said, if there are no interrupts, then the timer must be sufficiently big to count processor cycles precisely over the benchmark execution time without wrapping. Running CoreMark for at least two minutes on a device running at a higher clock frequency (e.g. 180MHz) will require a floating point variable to avoid wrapping, but on an FPGA with a slow clock it would not be so big.

Renesas DevCon

The biennial Renesas DevCon will be held in Orange County from October 12-15. EEMBC will be exhibiting and demoing its EnergyMonitor and ULPBench and discussing its upcoming IoT benchmark. EEMBC president, Markus Levy, also joins an illustrious panel of speakers for the topic of IoT security.

Light Reading’s Next Generation Network Components

Join Light Reading on November 5 in Santa Clara for a day of presentations and demonstration of Next Generation Network Components. EEMBC will be there with a tabletop exhibit. EEMBC members – contact Markus Levy to obtain your special discount code.

ARM TechCon

Bryan Chin (Cavium) and Markus Levy will co-present How (Not) to Generate Misleading Performance Results for ARM Servers at the ARM TechCon, taking place November 10-12 at the Santa Clara Convention Center.

Free Benchmark Downloads

• Free CoreMark^®-Pro download. CoreMark-Pro includes testing support for multicore technology, a combination of integer and floating-point workloads, and data sets for stressing larger memory subsystems.
• Trial version of BrowsingBench.
• Download AndEBench-Pro 2015 for free from Google Play™ and the Amazon™ Appstore for Android. As with all EEMBC benchmarks, the transparent availability of source code for AndEBench-Pro ensures that the benchmark is structurally sound and serves the industry’s demanding needs. Professional reviewers can contact EEMBC directly to obtain their specific version of AndEBench-Pro 2015 enabling them to change benchmarking parameters and gain access to even more detailed scoring information that is not disclosed with the standard benchmark.

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