PRESS RELEASE
Media Contact:
Jonah
McLeod
Andes
Technology Corporation
510
449 8634
jonahm@andestech.com
Andes Technology Corporation First Vendor to Use Official EEMBC
Certified CoreMark® Results to Reveal the Performance for Its
Entire CPU Product Line
All Andes CPU Cores Achieve Performance Results Exceeding 3 CoreMark/MHz
HSINCHU, Taiwan
– October 6, 2015 – Andes Technology Corporation, the leading Asia-based supplier of
small, low-power 32-bit embedded CPU cores, today announced that the EEMBC
Technology Center (ETC) has officially certified CoreMark
results for the company’s entire CPU product line. EEMBC certification ensures
that scores are repeatable, accurate, obtained fairly, and derived according to
EEMBC's rules. This certification is the most extensive carried out by any
EEMBC member and ranges from the 2-stage pipeline Andes N705 CPU core, which
achieved a CoreMark/MHz score of 3.32 to the 8-stage
pipeline Andes N1337 CPU core that achieved a CoreMark/MHz
score of 3.13 (see table below). The measurement of CoreMark/MHz
can provide a good initial comparison of how much power will vary between
different cores for the same level of performance.
“Andes is extremely
pleased to have completed the certification of all our cores on the CoreMark benchmark,” said Charlie Hong-Men Su, Ph.D. Andes
Technology CTO and Senior Vice President of R&D. “This represents the strength of our offering
based on our CPU cores and the latest compiler technologies, which we continue
to advance. Embedded applications where Andes cores find the greatest design
activity are unique in that they require high performance, low power
consumption, and small die size. CoreMark results, together
with achievable frequencies, provide our customers a good initial indication of
the amount of total performance each of our cores can achieve so they can
select the core with the smallest silicon footprint and lowest power
consumption to fit their end application. Once a customer selects a core, we
often work with them to measure performance for their specific application,
with the goal of keeping the power at a minimum. For example, a recent electronic shelf label
design win needed to operate for five years on battery power and they chose an
N801 core running 60 MHz.“
“I’m very impressed with the extensive list
of certified CoreMark results that Andes has revealed – clearly providing a great service to its
customers. Furthermore, Andes is the first EEMBC
member to have all of its processor cores certified for the CoreMark
benchmark,” said Markus Levy, EEMBC President. “As designers increase the
number of cores going into embedded applications, especially the ultra low-power Internet of Things, CoreMark
becomes less a measure of brute force performance and more a measure of the
right amount of performance for a specific design goal.”
|
Processor |
Pipeline stages |
CoreMark /MHz |
|
Andes N705 |
2 |
3.32 |
|
Andes N801 |
3 |
3.05 |
|
Andes E801 |
3 |
3.51 |
|
Andes N968A |
5 |
3.43 |
|
Andes N1068A |
5 |
3.75 |
|
Andes N1337 |
8 |
3.13 |
About the Coremark Benchmark
Built upon objective, clearly defined,
application-based criteria, the EEMBC CoreMark
benchmark reflects real-world applications and tests a processor’s basic
pipeline structure, as well as the ability to test basic read/write operations,
integer operations, and control operations. Over time, CoreMark
has replaced Dhrystone MIPS as the industry standard for measuring processor,
DSP, and compiler performance.
About
Andes Technology Corporation
Andes Technology Corporation is a
leader in developing high-performance/low-power 32-bit processors and its
associated SoC platforms to serve the rapidly growing
embedded system applications worldwide. The company’s broad and deep technical
expertise in microprocessor, system architecture, operating system, software
tool chain development, and SoC VLSI implementation
enables designers to shorten their time-to-market with quality designs. In
addition, Andes’ innovative configurable platform solution allows design teams
to construct unique system architecture and hardware/software partitioning to
achieve the optimal SoC. For more information about Andes, please visit
www.andestech.com.