Topics

• ARM Publishes EEMBC AutoBench and CoreMark Results for Cortex-R52
• Microchip Publishes Certified CoreMark Results for PIC32MM Family
• EEMBC Expands its In-house Testing Services
• EEMBC in the News
• EEMBC AutoBench 2.0 Ready to Go for Multicore
• On-Location with EEMBC

ARM Publishes EEMBC AutoBench and CoreMark Results for Cortex-R52

In conjunction with ARM’s recent announcement of its Cortex-R52 processor, the company certified and published results using the EEMBC AutoBench 1.1 benchmark suite. ARM also released CoreMark results for the R52. You can find this data within the myriad of related articles and EEMBC website.

The R52 demonstrates a considerable performance improvement over the ARM Cortex R5F. How much of the improvement can be attributed to the compiler? Also, EEMBC certified the R5F running at 190MHz on real hardware, whereas the R52 was certified running on simulation. How does the R52 performance scale up to full operating system?

While there was a very sizable increase in performance going from ARM Cortex R5F to ARM Cortex R52, the compiler version also changed from GHS 2015 to GHS v2017. How much of the performance gain can be attributed to the compiler optimizations versus architectural improvements? Most of the performance gain is from the core. ARM sees a small, but significant, uplift from the compiler (~5% on Cortex-R52 moving from 2015 to 2017 compilers).

EEMBC certified the R5F running on real hardware running at 190MHz (inside a Spansion device), whereas the R52 was certified on a 1MHz simulator. How will the AutoBench score scale as the R52 runs at real-world operating frequencies? AutoBench 1.1 is a fairly small benchmark, so this should scale fairly linearly to real operating frequencies. The system ARM simulated included a NIC and external memory system (assumed to be running at core speed), and the TCMs and caches were deliberately sized in such a way that the system is buildable by a silicon vendor. On the other hand, ARM has not yet run AutoBench 2.0, but it’s expected that the large dataset on that to show up with more memory system effects.

Microchip Publishes Certified CoreMark Results for PIC32MM Family

Microchip recently published certified CoreMark results for its PIC32MM0064GPL036, part of the company’s PIC32MM family. I asked Microchip to respond to a few questions.

• What are a few basic points about the PIC32MM0064GPL036 and family that are related to its performance factors?
• What were the primary reasons for certifying and publishing this device score?
• Compared to the PIC32MZ2048EFH144 @200Mhz (CM/MHz = 3.55) and PIC32MM0064GPL028 @24Mhz (3.62) that were coincidentally just published, what is significant about the score you just certified for PIC32MM0064GPL036 (CM/MHz = 3.16)?

1. What are a few basic points about the PIC32MM0064GPL036 and family that are related to its performance factors?
   1. This new family features a 0-wait state, cacheless architecture. This family also features a low-latency bus. While Microchip’s performance-maximizing PIC32MZ family allows the application to select between the MIPS32 ISA and the microMIPS ISA at the function level, the PIC32MM family saves power and cost by featuring the microMIPS ISA.
      
      
2. What were the primary reasons for certifying and publishing this device score?
   1. CoreMark is the gold standard for core benchmarking, replacing several ineffective, outdated benchmarks. Microchip certifies the results to ensure that they are reproducible by interested parties. This is the first device in the new low-power, low-cost PIC32MM family, so the community will be interested to see how the low-power features impact performance.

3. Compared to the PIC32MZ2048EFH144 @200Mhz (CM/MHz = 3.55) and PIC32MM0064GPL028 @24Mhz (3.62) that were coincidentally just published, what is significant about the score you just certified for PIC32MM0064GPL036 (CM/MHz = 3.16)?
   1. The certified 3.16 score uses the current v1.42 release of the MPLAB XC32 Compiler, which is based on GCC 4.8.3. The better 3.62 score uses GCC 4.9 and represents what is possible for the platform. MPLAB XC32 typically lags behind the latest GCC releases by a few versions in order for bugs in newer releases to be ironed out.

EEMBC Expands its In-house Testing Services

The EEMBC Technology Center benchmark testing services include porting the benchmarks to the target platform(s), running the benchmarks and reporting scores, comparing different hardware platforms and different hardware configurations, and comparing different tool chains and different optimization options. Read more…

EEMBC AutoBench 2.0 Ready to Go for Multicore

EEMBC’s AutoBench 2.0 suite is available now to members and nonmember licensees. AutoBench 2.0 delivers a multicore-intense upgrade from the consortium’s long-standing automotive/industrial benchmark suite. For more information.

EEMBC in the News

•   ARM Focuses On Self-Driving Cars With Cortex-R52. Source: AndroidHeadlines (09/21/16)
•   ARM reveals R52 core for highest functional safety standards. Source: EDN Europe (09/21/16)
•   ARM Cortex-R52 advanced safety processor launched. Source: Hexus (09/21/16)
•   ARM Cortex-R52: Neuer Prozessor soll Autos sicherer Machen. Source: Notebook Check (09/21/16)
•   ARM Cortex R52: Fuhrt sicherheitsrelevanten Code unabhangig und geschutzt vor anderen Programmen aus.Source: Tom's Hardware Germany (09/21/16)
•   ARM Kembangkan Cortex-R52 untuk Kendaraan Self-Driving. Source: TeknoJurnal (09/21/16)
•   ARM、自律自動走行車両の実現に向けた機能安全プロセッサ「Cortex-R52」発表会 (09/21/16)
•   ARM Cortex R52 with AutoBench and CoreMark Results. Source: AnandTech (09/20/16)
•   ARM Cortex-R52 processor for self-driving cars with AutoBench and CoreMark Results. Source: VentureBeat (09/20/16)
•   ARM core for autonomous vehicles. Source: Electronics Weekly (09/20/16)
•   ARM sort son premier processeur base sur l'architecture ARMv8-R. Source: L'Embarque (09/20/16)
•   Arm slapper realtidskarna. Source: Elektronik Tidningen (09/20/16)
•   ARM zeigt sicheres Chip-Design fur autonome Fahrzeuge und medizinische Gerate. Source ZDNet (09/20/16)
•   ARM Cortex-R52, il "cugino" di A10 e destinato alle auto a guida autonoma. Source: macitynet.it (09/20/16)
•   面向无人驾驶，ARM推出最先进的安全处理器. Source: laoyaoba.com (09/20/16)
•   ARM desenvolve chip especifico para carros autonomos. Source: canaltech.com.br (09/20/16)
•   ARM Cortex-R52 fur funktionale Sicherheit. Source: Elektroniknet.de (09/20/16)
•   Benchmark ULPBench entzaubert (09/20/16)
•   AutoBench 2.0-Les processeurs multicoeurs pour l'automobile ont d (08/19/16)
•   AutoBench 2.0-EEMBC MultiBench launches new industry standard targeting automotive multicore systems (08/16/16)
•   AutoBench 2.0-EEMBC updates automotive benchmark for scalability tests (08/15/16)
•   AutoBench 2.0-EEMBC Upgrades Auto Benchmarks in Microprocessor Report (08/15/16)

On Location With EEMBC

EEMBC@IoT Tech Expo

The IoT Tech Expo on October 20-21 at the Santa Clara Convention Center. EEMBC president, Markus Levy, joins a panel discussion ‘The Future of IoT Development’ and will present “Battery-life and Performance Analysis of Communication and Security for Things of the IoT”. This 2-day conference and event will host case studies and dedicated tracks covering Smart Cities, Connected Living, Wearables, Developing & IoT Technologies, Connected Industry, Connected Services and Data & Security.

ARM TechCon

At the ARM TechCon, join EEMBC president, Markus Levy, and DELL senior systems engineer, Rory Rudolph, as they present "Understanding IoT Gateway Performance Analysis". For a complete schedule of sessions, go to http://schedule.armtechcon.com/list