Topics
- Upcoming CoreMark™ Webinar
- Deep Packet Inspection Benchmark Project Update
- Update on BrowsingBench™
- New Certified EEMBC Benchmark Scores
- New CoreMark™ Scores
- Upcoming Events and Recent News Items
Upcoming
CoreMark™ Webinar
“Using CoreMark™ to Demonstrate
Performance-Related MCU Features and Compiler Tradeoffs”
Hosted
by Markus Levy, EEMBC President.
Presented by: Shay Gal-On;
EEMBC Director of Software Engineering and
Olivier Kaps,
STMicroelectronics Architecture and Support Engineer
CoreMark™ is well on its way to becoming the defacto standard benchmark for microcontroller performance analysis. This is why EEMBC members, such as STMicroelectronics, are using CoreMark to demonstrate the features and benefits of their microcontroller products. In this webinar, we'll begin with an introduction to the CoreMark™ basics, and then launch into a demonstration that shows the capabilities of the Adaptive Real Time "ART" Accelerator of the STM32 F-2 series, as well as tradeoffs based on compiler selection. The ART Accelerator allows the microcontroller to execute code from flash with a performance equivalent to 0 wait-states at 120MHz. In the process, we'll go over the setup of the benchmarking environment including the build options and compiler flags. We'll wrap up the webinar with a short discussion on how CoreMark™ ties in to the overall methodology on benchmarking embedded processors.
Date:
February 22, 2011
Time: 9:00 AM PST
Register by February 21
Deep
Packet Inspection (DPIBenchTM)
Benchmark Project
Chaired by Jeff Caldwell
of SonicWALL, the DPIBench™ working group continues to move forward
on development of its suite of network security performance
benchmarks for measuring DPI product throughput. Recently, the
working group submitted a request to a variety of test equipment
vendors to verify whether their equipment could handle the
DPIBench™ workload requirements.
White paper on this topic.
Membership in
this working group is $2500 for the first year. If you are
interested in joining, please
contact Markus
Levy, EEMBC president.
Update on
BrowsingBench™
BrowsingBench™,
a benchmark to measure the user’s browser experience, is
nearing final release. This benchmark utilizes a unique approach
previously unavailable in any browser-related benchmark.
Participation
is open to all EEMBC Consumer subcommittee and Board of Directors
members. For further information on joining, please contact Markus
Levy, EEMBC president.
New Certified EEMBC Benchmark Scores
Freescale Semiconductor released certified EEMBC AutoBench results for its Power Architecture based Qorivva microcontrollers (utilizing Green Hills: PPC Version 5.20 compiler). The Qorivva 32-bit MPC5674F achieved a benchmark score of 305 Automarks, and Freescale's MPC564xA and MPC5566 MCUs scored 150 and 121 Automarks, respectively. View the scores.
New
CoreMark™ Scores
More than
3000 users have downloaded the CoreMark™ benchmark, with more than 200 scores posted to the website. Since
our previous newsletter, users have posted CoreMark™ scores for the
following processor/compiler combinations:
Processor |
Compiler |
AMD K6-2 500 MHz |
GCC4.1.0 20060304 (Red Hat 4.1.0-3) |
ARMv7 Processor rev 3 (v7l) 600 MHz |
Android NDK-r5 (GCC 4.4.3) |
Infineon TC1796-256F150E BE 150MHz |
GCC 3.4.5 (HighTec) |
Intel Core 2 Duo T7200 2000MHz |
GCC3.4.4 (cygming special, gdc 0.12, using dmd 0.125) |
Intel Core i5 CPU M 560 2667MHz |
gcc version 4.4.5 (Gentoo 4.4.5 p1.0, pie-0.4.5) |
Intel Core i5-650 3200Mhz |
GCC4.4.5 |
Marvell Kirkwood 88F6282 (ARMADA 300) 2000MHz |
GCC4.4.5 |
Microchip PIC32MX440F512H 80MHz |
GCC3.4.4 Microchip MPLAB C Compiler for PIC32 MCUs v1.10(b) |
Microchip PIC32MX795F512L 96MHz |
Sourcery G++ 2010.09-32 (GCC4.5.1) |
Renesas SH7040 - HD6437043A romless 1.4.7MHz |
Renesas (Hitachi) SH SERIES C Compiler Ver. 3.0g |
Renesas SH7206 - R5S72060W200FPV 176.9MHz |
Renesas SH SERIES C/C++ Compiler V.9.00.01.001 |
STM32F107VBT6 10MHz |
GCC 4.4.1 (CodeSourcery Lite) |
Tilera TILEPro64 (TLR36480BG-9C) 866Mhz |
gcc 4.4.3 |
Upcoming
Events and Recent News
EEMBC will be
exhibiting in the STMicroelectronics booth at Embedded
World, taking place on March 1-3 in Nurnberg,
Germany. Drop by and visit us and check out the cool CoreMark and
EnergyBench demonstration.
CoreMark™:
A realistic way to benchmark CPU performance, by
Shay Gal-On and Markus Levy . EETimes. 02/01/11
How
are competitors differentiating Cortex-M3 based mcus? ,
by Graham Pitcher. NewElectronics. 01/10/11
STM32
F-2 MCUs exploit Cortex-M3 performance, by Colin
Holland. EETimes. 11/30/10
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