Winter 2008
EEMBC News Briefs
The EEMBC Board of Directors has three new members: RMI, MediaTek, and Cavium Networks. Huawei has also joined the Consortium as a member of the Networking Subcommittee.
EEMBC is now working on a new hypervisor benchmark suite that will measure the contribution of hypervisors, also known as virtual machine managers, to performance, code size, and energy consumption in a wide range of embedded systems. The new Hypervisor Working Group is being headed up by Frank Altschuler, director of marketing for TRANGO Virtual Processors.
A new benchmark testing service from the EEMBC Technology Center (ETC) in Sunnyvale, Calif., allows any company to make EEMBC benchmark testing an integral part of its product development and release process — without tying up internal engineering resources. Services include porting and running the benchmarks, performance analysis, and preparation of platforms for benchmark score certification. Click for more information.
Plan to attend the EEMBC sponsored luncheon on April 1 at the Multicore Expo
The next meeting of the EEMBC Board of Directors and Working Groups will take place April 9 and 10 in Las Vegas at The Venetian. Viva Las Vegas!
| Letter from the President |
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Recently, I was invited to chair a special standards meeting in Detroit on automotive benchmarks as well as strategies to help facilitate the adoption of multicore technology in the automotive industry. What made this all-day meeting most interesting was that it was hosted by General Motors and the attendees were 64 technical people representing leaders in the automotive industry: ARM, Atmel, Autoliv, Bosch, Chrysler, Continental, Delphi, Denso, dSpace, Elektrobit, eSol, ETAS, Ford, Freescale, Fujitsu, GM, Green Hills Software, Hella, Hitachi, Infineon, Mathworks, Microchip, MIPS, National Instruments, NEC, PolyCore Association, QNX, Renesas, Siemens VDO, ST Microelectronics, Texas Instruments, Toshiba, Vector, Wind River, and Xilinx. The morning session focused on automotive benchmarking with the primary goals of understanding the differences and similarities in benchmarking different automotive application areas and to build consensus on a plan of action for building these benchmarks. The afternoon session dealt with multicore technology and the primary goals of defining and identifying key areas that would benefit from standardization for safety, scheduling, task and resource management, communications, and availability. Out of the benchmarking discussion, we confirmed that powertrain is definitely the most challenging area to standardize on for benchmarking. One of the biggest hurdles is... more.. Markus Levy |
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By Shay Gal-On, Director of Software Engineering
| After nearly two years of discussion, debate, design, development, and testing, our first generation MultiBench™ multicore benchmark software is complete and ready to rip apart any and all symmetrical multicore processors. As a matter of fact, the initial results that we're seeing in the lab are clearly demonstrating that no matter how 'beefy' the multicore processor, there is always some sort of bottleneck. The practical side of this is that the system developer will also likely encounter these bottlenecks.
Putting multiple execution cores into a single processor does not guarantee greater multiples of processing power. However, the right combination of processor and programming techniques can scale well with the number of cores. But the bottom line is... more |
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Linley Tech Seminar On March 19 in San Jose, The Linley Group presents a Linley Tech Seminar focused on CPU cores and licensable intellectual property (IP) for networking and communications applications. This one-day event delivers a wealth of information including technology trends, tips, and traps in using and understanding the IP blocks available from leading vendors. If you are using or evaluating advanced IP for your ASIC or SoC (systems on a chip) device designs, this seminar is for you. A presentation by Shay Gal-On, EEMBC’s director of software engineering, will highlight EEMBC's multicore benchmark strategy, using data obtained from actual processor tests to show how various workload combinations affect performance in multicore designs. The goal is to determine CPU, memory, and operating system bottlenecks. Shay will also discuss requirements for testing the performance of next-generation SoCs in networking and telecomm applications. The event is free to qualified ASIC and SoC designers at chip suppliers and OEMs. More.. MicroTCA Summit |
