EEMBC^® MultiBench™ Multicore Benchmarks Ready for Member Certification

MIPS Technologies is First EEMBC Member
to Certify on Multicore Platform

EL DORADO HILLS, Calif. — March 11, 2009 — The Embedded Microprocessor Benchmark Consortium today announced the availability of MultiBench 1.0e, the official certification version of its MultiBench^TM multicore benchmark software. Beyond helping designers to optimize programs for specific processors and systems, MultiBench allows users to assess the impact of memory bottlenecks, OS scheduling support, efficiency of synchronization, and other related functions in systems using multicore processors.

In preparation for the release of MultiBench 1.0e, EEMBC made several enhancements to its MultiBench 1.0 benchmark software. The first enhancement is a mechanism that automatically calculates the MultiBench marks, a set of consolidated scores for a given device which is based on individual scores in a group of related workloads. The MultiBench marks include Parallelmark^TM, Mixmark^TM, and Multimark^TM, each of which is designed to highlight a specific aspect of multicore performance, such as scalability and overall throughput.

In the second enhancement, EEMBC has included an additional option for workload data sizes. MultiBench 1.0 contained workloads with 64Mbyte data sizes, while the certification version uses datasets that limit the working set size to 4Mbytes per context. This is significant because the use of 64Mbyte data sizes can easily exceed the memory capacity of the majority of embedded multicore platforms, especially when MultiBench is running with multiple degrees of concurrency. The smaller 4Mbyte data sizes also make MultiBench more practical to run on software-based simulators.

Benchmark score certification is an integral part of the EEMBC structure. The EEMBC Technology Center (ETC) performs certifications to verify the accuracy and repeatability of benchmark scores, disclosure reports, and other data submitted by member companies. ETC performed the first MultiBench 1.0e certification on MIPS Technologies’ MIPS32^® 1004K™ Coherent Processing System (CPS), a multi-threaded multiprocessor IP core.

“Although it’s not a requirement for EEMBC members to certify, certification adds an extra level of assurance that the scores are repeatable and are generated according to the rules established by the consortium,” said EEMBC Director of Software Engineering Shay Gal-On. “Although we designed the MultiBench infrastructure to run in an automated manner, we still encourage EEMBC members to take advantage of this service that is included with their membership.”

MultiBench targets the evaluation of scalable symmetrical multicore processor (SMP) architectures with shared memory. It uses a thread-based API to establish a common programming model. The suite’s individual benchmarks target three forms of concurrency: data decomposition, multiple data stream processing, and the processing of multiple workloads. Data decomposition allows multiple threads to cooperate on achieving a unified goal and demonstrates a processor’s support for fine grain parallelism. Processing of multiple data streams uses common code running over multiple threads and demonstrates how well a solution can scale over scalable data inputs. Finally, multiple workload processing shows the scalability of a solution for general-purpose processing and demonstrates concurrency over both code and data.

EEMBC’s MultiBench 1.0e multicore-enabled benchmarks are available for licensing now. The EEMBC Technology Center offers analysis of MultiBench results as one of its testing services. Further information is available at www.eembc.org.

About EEMBC

EEMBC, the Embedded Microprocessor Benchmark Consortium develops benchmark software that helps processor architects and embedded system designers better understand the capabilities of embedded microprocessors and the systems in which they are used. Currently available benchmark software allows users to predict unicore and multicore processor performance and its associated energy cost in digital entertainment, digital imaging, networking, and office automation applications. Additional suites address automotive, embedded Java, and telecom applications. The consortium’s operations include an EEMBC Technology Center that provides a full range of benchmarking and benchmark score certification services in addition to serving as EEMBC’s R&D center for benchmark software development.

EEMBC’s members include AMCC, AMD, Analog Devices, ARM, Broadcom, Cavium Networks, Centaur Technology , CEVA, Code Sourcery, Cypress Semiconductor, EEMBC, esmertec, Faraday, Freescale Semiconductor, Fujitsu Microelectronics, Green Hills Software, Huawei Technologies Co, IAR Systems AB, IBM, Imagination Technologies, Infineon Technologies, Intel, LSI, LynuxWorks, Marvell Semiconductor, MediaTek, Mentor Graphics, Microchip Technology, MIPS Technologies, National Instruments, NEC Electronics, Nokia, NXP Semiconductors, OKI Semiconductor, Open Kernel Labs, Panasonic, Qualcomm, Realtek Semiconductor, Red Hat, Renesas Technology, RMI, Samsung Electronics, Sony Computer Entertainment, ST Microelectronics, Sun Microsystems, Texas Instruments, Toshiba, VirtualLogix, VMware, and Wind River Systems.

EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium. All other trademarks appearing herein are the property of their respective owners.