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EEMBC Member List |
Academic Members | Academic License |
Academic Research |
| The EEMBC Academic licensees listed below have graciously agreed to share their research interests relative to EEMBC benchmarks. |
Chalmers University of Technology Dept. of Computer Science and Engineering Per Stenstrom The research we are doing based on EEMBC focuses on two topics. 1. We are doing research in a new class of reconfigurable architectures for the embedded space that promises to exhibit high energy-efficiency and performance while at the same time being able to adapt to workloads. We want to use EEMBC to evaluate this new architectural style which we have called FlexSoC. 2. We are also doing research in novel programming interfaces for multicore architectures. To this end, we are specifically interested in how well emerging transactional memory models can help applications in the embedded space to leverage on the compute power of multicores. We are using EEMBC to quantitatively provide empirical data for this. |
Dongguk University Korea Kangwoo Lee My fundamental research interest lies in Computer Architecure. Previously, for the last decades or so, I was studying the memory architecture including caches in multiprocessor systems. The application domain for such systems are scientific computations and commercial applications. For the scientific applications, Stanford's SPLASH benchmark suites and, for the commercial applications, TPC benchmarks were used. Recently, I have become interested in embedded system architectures and printer systems in particular. Having licensed the EEMBC Office Automation benchmarks, I will be doing performance evaluations for a certain commercial printer system. The goal of the research is to find a methodology for designing best-performing and well-tuned printer systems. In addition, I have formed a team with my colleagues to study embedded systems for mobile systems. Networking and communication issues will be included. |
Ecole Polytechnique Federale de Lausanne Paolo Ienne Processor Architecture Laboratory (LAP) At LAP (Processor Architecture Laboratory) we perform research in the area of innovative embedded-system architectures, including automated instruction set extensions, low-power memory hierarchies, and multiprocessor-on-chip. |
Friedrich-Schiller University of Jena, Germany Wolfram Amme Here is a description of our |
Harz University Prof. Dr. Klaus-Dietrich Kramer |
Kyoto University Taiichi Yuasa We are developing real-time garbage collection algorithms for embedded systems. We have developed return barrier GC replication-based incremental compaction algorithms. We implemented them on a Java VM for mobile phones and evaluated it using EEMBC GrinderBench benchmarks. Now we modifying the algorithm to improve its performance. Publications: H. Saiki, Y. Konaka, T. Komiya, M. Yasugi, and T. Yuasa. "Real-time GC in JeRTy VM using the return-barrier method". In Proceedings of ISORC 2005, pages 140-148. T. Ugawa, M. Yasugi, and T. Yuasa. "Replication-Based Incremental Compaction". In Proceedings of ISORC 2008, pages 516-526. |
La Trobe University Center for Technology Infusion Jugdutt (Jack) Singh Aniruddha Desai We are developing a configurable architecture for a hardware-based Java processor for real-time and portable applications. We use EEMBC benchmarks for workload characterization and performance evaluation of our design. |
Manchester Metropolitan University Computing Science Andy Nisbet I will be working on value reuse and value locality optimizations for embedded processor architectures. |
Nanyang Technological University, Singapore CHiPES Thambipillai Srikanthan Centre for High Performance Embedded Systems (CHiPES) CHiPES is involved in the research and development of high performance embedded systems. Current research areas include design methodologies for constraint-aware techniques, reconfigurable computing, embedded software, and architectural translations of complex algorithms. |
National Taiwan University CSIE Chi-Sheng Shih We are using EEMBC benchmarks to evaluate our design of an embedded real-time operating systems on multi-core SoC systems. The systems is still in progress and should have our preliminary results in mid-2008. |
National Tsing Hua University Computer Science Jenq-Kuen Lee The research we are doing based on EEMBC is mainly on the compiler technologies for VLIW DSP processors, especially for the family of DSP processors with distributed register files and multi-bank register files. To reduce the design complexity and power consumptions of VLIW DSP processors, distributed register files and multi-bank register architectures are used to reduce the amount of read/write ports needed. In addition, the register files shared by multiple functional units might not be accessible to a particular functional unit at all times to further reduce the amount of read and write ports by taking advantage of DSP application characteristics. The appearance of VLIWDSP processors with highly fragmented register file designs presents a great challenge for compilers to generate efficient codes for multimedia applications. Advanced compiler optimization techniques currently being developed in our group for such architectures include SIMD optimization schemes, low-power compiler optimization schemes, SWP schemes for distributed register files, and programming models for multi-core DSP environments. We are using the EEMBC benchmarks to evaluate the performance of our optimizing compiler schemes. |
Northeastern University David Kaeli We are using EEMBC to investigate how to balance performance and power of the Blackfin BF53x embedded environment by exploiting the availability of the performance counters on the Blackfin. We are running the EEMBC benchmarks while applying profile-guided dynamic voltage and frequency scaling on the embedded system and trying to reduce the DSP's energy consumption without significant performance degradation. |
PUSAN National University Bumjoo Shin Currently, my research interest is to improve performance of a non-commercial JVM. |
RWTH Aachen University Software for Systems on Silicon (SSS) Rainer Leupers We use EEMBC as benchmark in our research on application specific instruction set processor (ASIP) design tools and automated instruction set customization. |
Toulouse Laboratoire d'Analyse et d'Architecture des Syst Jacques Collet We are studying the execution variability of automotive applications. By execution variability, we mean the dispersion of the execution times, which depends on many factors, for instance: |
TU Braunschweig IDA Rolf Ernst Joern Christian Braam Current automotive embedded systems are highly complex due to advanced functionality which is often distributed over many networked electronic control units. Because there is a wide variety of available processors with different strengths, the challenge is to make an optimal selection as early as possible. This decision should be taken early because that enables an early start of the SW development and saves money. With our Wormhole project we are focusing on the timing aspect. Our approach is based on a virtual machine. This virtual machine is realized by a generic simulator with a parameterized micro architecture and instruction set architecture. During training runs with benchmarks the virtual machine parameters are adapted to the properties of a real machine. The idea is to perform that characterization once and then use the adapted generic simulation in several projects. It is not possible nor intended to perform a point estimation similar to a cycle accurate simulator. Instead of that we are looking for multiple sets of HW parameters which bound the performance behaviour of one real HW with a predefined tolerance. Because these benchmarks have to cover as many SW characteristics as possible we use the EEMBC benchmark suite. This suite is a good representation of the typical SW behaviour of different domains. To restrict the computation time of the search it is controlled by statistical bounds, e.g., the deviation. So, an early HW exploration can be performed or potential HW candidates are identified. In any case the candidates are investigated in later design step with more accurate but more expensive methods, mainly measurements with cycle accurate simulators and the respective development tools. |
UC Berkeley David Patterson We are examining whether seven or so kernels can capture the essence of future parallel computation in many different arenas. We use EEMBC to see how well these kernels cover the embedded computing arena. |
University of Aizu Hitoshi Oi The areas of my interest are computer architecture, workload analysis, and performance evaluation. I have been using GrinderBench from EEMBC to evaluate techniques to improve the performance of Java Virtual Machine for embedded platforms. |
University of Augsburg Institute of Computer Science Theo Ungerer Our research in the embedded systems research group of University of Augsburg focuses on hard real-time capable design of embedded processors and system software. The EEMBC benchmarks are used for comparison of simulated research prototypes within the CAR-SoC project (see: http://www.informatik.uni-augsburg.de/en/chairs/sik/research/embedded/carsoc/) and will also be distributed to the partners within the HiPEAC Network of Excellence cluster on Multithreaded Real-time of the European Community that perform research based on the CAR-SoC processor prototype. |
University of Hertfordshire School of Computer Science Colin Egan We use the EEMBC in one of the most important areas of contemporary research in computer engineering: energy efficiency. We focus our work onto reducing the energy efficiency of costly branch predictors by dynamically hand-shaking profiled static predictions/branch removal together with a low energy branch predictor. We demonstrate that the majority predictor accesses and predictor updates are not necessary, thereby achieving saving significant amounts of energy. Our work also shows that the use of costly predictors in terms of both energy and silicon space is also not necessary. |
University of Michigan Electrical Engineering & Computer Science Trevor Mudge We are involved in some research with ARM in which we are using EEMBC benchmarks. |
University of North Texas Krishna Kavi We have used subsets of the EEMBC benchmarks, as well as similar benchmarks, to evaluate optimal cache configurations. See the following publications: A. Naz, K. Kavi, W. Li and Philip Sweany. "Tiny split data caches make big performance impact for embedded applications," the Journal of Embedded Computing (Special Issue on Embedded Single-Chip Multi-core Architectures from System Design to Application Support), Vol.2, No.2, pp 207-219, November, 2006. Afrin Naz, Krishna Kavi, JungHwan Oh and Pierofranco Foglia. "Reconfigurable split data caches: A novel scheme for embedded systems," Proceedings of the 22nd Annual ACM Symposium on Applied Computing, Seoul, Korea, March 11-15, 2007, pp 707-7112. Afrin Naz, Krishna Kavi, Philip Sweany and Wentong Li. "A study of reconfigurable split data caches and instruction caches," Proceedings of the 19th ISCA Parallel and Distributed Computing Systems, Sept 20-22, 2006, San Francisco, CA. |
University of Paderborn Ulrich Rueckert |
University of Rochester Martin Margala My primary research interests are in reconfigurable parallel low energy high throughput architectures and design for reliability of multi-gigahertz circuits and systems. |
University of Texas at Austin Department of Computer Sciences Doug Burger We are working on designing novel, power-efficient microprocessor architectures for high-performance embedded computing. With my colleagues. We have developed the TRIPS architecture, which defines a new instruction set and efficient, sixteen-wide-issue micro-architecture. |
University of Toronto Jonathan Rose J. Gregory Steffan Peter Yiannacouras We are using the EEMBC benchmarks to evaluate the performance of processor-based systems which are implemented on FPGAs. We attempt to leverage the programmability in the device to tailor the processor to the designer's speed, area, and power/energy requirements. The EEMBC benchmarks provide us with credible performance measurements which match the rigor with which we attain area, clock frequency, and power/energy measurements. |
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